/* linux/include/asm-arm/arch-at91sam9260/at91sam9260_shdwc.h
 * 
 * Hardware definition for the shdwc peripheral in the ATMEL at91sam9260 processor
 * 
 * Generated  12/07/2006 (15:04:00) AT91 SW Application Group from SHDWC_6122A V1.3
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9260_SHDWC_H
#define __AT91SAM9260_SHDWC_H

/* -------------------------------------------------------- */
/* SHDWC ID definitions for  AT91SAM9260           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_SYS
#define AT91C_ID_SYS   	 1 /**< System Controller id */
#endif /* AT91C_ID_SYS */

/* -------------------------------------------------------- */
/* SHDWC Base Address definitions for  AT91SAM9260   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SHDWC     	0xFFFFFD10 /**< SHDWC base address */

/* -------------------------------------------------------- */
/* PIO definition for SHDWC hardware peripheral */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* Register offset definition for SHDWC hardware peripheral */
/* -------------------------------------------------------- */
#define SHDWC_SHCR 	(0x0000) 	/**< Shut Down Control Register */
#define SHDWC_SHMR 	(0x0004) 	/**< Shut Down Mode Register */
#define SHDWC_SHSR 	(0x0008) 	/**< Shut Down Status Register */

/* -------------------------------------------------------- */
/* Bitfields definition for SHDWC hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register SHDWC_SHCR */
#define AT91C_SHDWC_SHDW      (0x1 << 0 ) /**< (SHDWC) Processor Reset */
#define AT91C_SHDWC_KEY       (0xFF << 24) /**< (SHDWC) Shut down KEY Password */
/* --- Register SHDWC_SHMR */
#define AT91C_SHDWC_WKMODE0   (0x3 << 0 ) /**< (SHDWC) Wake Up 0 Mode Selection */
#define 	AT91C_SHDWC_WKMODE0_NONE                 0x0 /**< (SHDWC) None. No detection is performed on the wake up input. */
#define 	AT91C_SHDWC_WKMODE0_HIGH                 0x1 /**< (SHDWC) High Level. */
#define 	AT91C_SHDWC_WKMODE0_LOW                  0x2 /**< (SHDWC) Low Level. */
#define 	AT91C_SHDWC_WKMODE0_ANYLEVEL             0x3 /**< (SHDWC) Any level change. */
#define AT91C_SHDWC_CPTWK0    (0xF << 4 ) /**< (SHDWC) Counter On Wake Up 0 */
#define AT91C_SHDWC_WKMODE1   (0x3 << 8 ) /**< (SHDWC) Wake Up 1 Mode Selection */
#define 	AT91C_SHDWC_WKMODE1_NONE                 (0x0 <<  8) /**< (SHDWC) None. No detection is performed on the wake up input. */
#define 	AT91C_SHDWC_WKMODE1_HIGH                 (0x1 <<  8) /**< (SHDWC) High Level. */
#define 	AT91C_SHDWC_WKMODE1_LOW                  (0x2 <<  8) /**< (SHDWC) Low Level. */
#define 	AT91C_SHDWC_WKMODE1_ANYLEVEL             (0x3 <<  8) /**< (SHDWC) Any level change. */
#define AT91C_SHDWC_CPTWK1    (0xF << 12) /**< (SHDWC) Counter On Wake Up 1 */
#define AT91C_SHDWC_RTTWKEN   (0x1 << 16) /**< (SHDWC) Real Time Timer Wake Up Enable */
#define AT91C_SHDWC_RTCWKEN   (0x1 << 17) /**< (SHDWC) Real Time Clock Wake Up Enable */
/* --- Register SHDWC_SHSR */
#define AT91C_SHDWC_WAKEUP0   (0x1 << 0 ) /**< (SHDWC) Wake Up 0 Status */
#define AT91C_SHDWC_WAKEUP1   (0x1 << 1 ) /**< (SHDWC) Wake Up 1 Status */
#define AT91C_SHDWC_FWKUP     (0x1 << 2 ) /**< (SHDWC) Force Wake Up Status */
#define AT91C_SHDWC_RTTWK     (0x1 << 16) /**< (SHDWC) Real Time Timer wake Up */
#define AT91C_SHDWC_RTCWK     (0x1 << 17) /**< (SHDWC) Real Time Clock wake Up */

#endif /* __AT91SAM9260_SHDWC_H */
